The present invention relates to a nonvolatile semiconductor memory using a ferroelectric capacitor for controlling the gate potential of a field effect transistor (FET).
In a conventional nonvolatile ferroelectric memory using a ferroelectric capacitor for controlling the gate potential of a FET, a source region 2 and a drain region 3 are formed in a silicon substrate 1 and a silicon oxide film 5 serving as a dielectric film is formed on a channel region 4 formed between the source region 2 and the drain region 3 in the silicon substrate 1 as shown in FIG. 4. A ferroelectric film 6 of a metal oxide such as lead zirconate titanate (PZT) or bismuth tantalatexe2x80x94strontium (SBT) is formed on the silicon oxide film 5, and a gate electrode 7 is formed on the ferroelectric film 6.
In the ferroelectric memory, upward or downward polarization can be caused in the ferroelectric film 6, and the depth of the surface potential of a region in the silicon substrate 1 below the gate electrode 7 can be set to two different values respectively corresponding to the two polarized states of the ferroelectric film 6.
In this case, the depth of the surface potential of the region in the silicon substrate 1 below the gate electrode 7 (namely, the channel region) controls the resistance between the source region 2 and the drain region 3, and hence, the resistance between the source region 2 and the drain region 3 is set to a large value or a small value correspondingly to the polarization direction of the ferroelectric film 6. These states are kept (stored) as far as the polarization of the ferroelectric film 6 is kept, and thus, the ferroelectric memory works as a nonvolatile memory.
For storing any of two logic states in the ferroelectric memory or reading any of the two logic states from the ferroelectric memory, for example, the downward polarized state of the ferroelectric film 6 is assumed logic xe2x80x9c1xe2x80x9d and the upward polarized state thereof is assumed logic xe2x80x9c0xe2x80x9d.
In order to turn the polarization of the ferroelectric film 6 downward to write a data (of logic xe2x80x9c1xe2x80x9d) in the ferroelectric memory, a large positive voltage is applied to the gate electrode 7 with the silicon substrate 1 set to the ground potential. On the other hand, in order to turn the polarization of the ferroelectric film 6 upward to write a data (of logic xe2x80x9c0xe2x80x9d) in the ferroelectric memory, a large negative voltage is applied to the gate electrode 7 with the silicon substrate 1 set to the ground potential. Thereafter, the potential of the gate electrode 7 is rapidly changed to the ground potential due to a junction leakage current of the FET, namely, a potential difference between the gate electrode 7 and the silicon substrate 1 is rapidly eliminated, and thus, the written data is kept.
The data storage state of the ferroelectric memory will now be described with reference to energy band diagrams of FIGS. 5A and 5B.
It is assumed, for example, that the silicon substrate 1 has the p-type conductivity and the source region 2 and the drain region 3 have the n-type conductivity. FIG. 5A shows energy band obtained in the ferroelectric memory by applying a positive bias voltage to the gate electrode 7 so as to turn the polarization of the ferroelectric film 6 downward (namely, to write a data of logic xe2x80x9c1xe2x80x9d) and then changing the potential of the gate electrode 7 to the ground potential. FIG. 5B shows energy band obtained in the ferroelectric memory by applying a negative bias voltage to the gate electrode 7 so as to turn the polarization of the ferroelectric film 6 upward (namely, to write a data of logic xe2x80x9c0xe2x80x9d) and then changing the potential of the gate electrode 7 to the ground potential. In FIGS. 5A and 5B, a reference numeral 30 denotes the direction of polarization, a reference numeral 31 denotes the conduction band of the gate electrode 7, a reference numeral 32 denotes the energy band of the ferroelectric film 6, a reference numeral 33 denotes the energy band of the silicon oxide film 5, a reference numeral 35 denotes an n-type conduction channel and a broken line denotes the Fermi level.
When the polarization of the ferroelectric film 6 is downward, a negatively ionized depletion layer extends to a deep region of the silicon substrate 1. Therefore, as shown in FIG. 5A, the n-type conduction channel 35 is formed in the region in the silicon substrate 1 below the gate electrode 7 (namely, in the channel region 4), and hence, the surface potential of the silicon substrate 1 is lower than the ground potential.
On the other hand, when the polarization of the ferroelectric film 6 is upward, holes, that is, p-type carriers, are stored in the region in the silicon substrate 1 below the gate electrode 7 (namely, in the channel region 4) and hence the n-type conduction channel is not formed in the channel region 4 as shown in FIG. 5B. Therefore, the surface potential of the silicon substrate 1 accords with the ground potential.
The surface potential of the region in the silicon substrate 1 below the gate electrode is thus different depending upon the polarization direction of the ferroelectric film 6. Therefore, when a potential difference is caused between the drain region 3 and the source region 2, a current depending upon the polarization direction flows between the drain region 3 and the source region 2. Specifically, when the surface potential of the silicon substrate 1 is lower than the ground potential (which corresponds to logic xe2x80x9c1xe2x80x9d), the resistance between the drain region 3 and the source region 2 is low (which corresponds to an on-state) so that a large current can flow. When the surface potential of the silicon substrate 1 accords with the ground potential (which corresponds to logic xe2x80x9c0xe2x80x9d), the resistance between the drain region 3 and the source region 2 is high (which corresponds to an off-state) so that a current can minimally flow. Accordingly, it can be determined that the ferroelectric memory is in an on-state (corresponding to logic xe2x80x9c1xe2x80x9d) or an off-state (corresponding to logic xe2x80x9c0xe2x80x9d) by measuring the magnitude of the current flowing between the drain region 3 and the source region 2.
In this manner, the logic state of the ferroelectric memory can be read by causing a potential difference between the source and the drain without applying a bias voltage to the gate electrode 7. Accordingly, the on-state of the ferroelectric memory corresponds to a depletion state of a MOS transistor.
After writing a data in the ferroelectric memory, a positive or negative bias voltage is inevitably generated in the ferroelectric film 6 as shown in FIGS. 5A and 5B. The silicon oxide film 5 and the silicon substrate 1 are supplied with potentials so as to cancel the bias voltage, and whether the ferroelectric memory is in an on-state or off-state depends upon the thus supplied potentials.
The ferroelectric film 6 is an insulating film and has resistivity of approximately 1015 xcexa9xc2x7cm at most. Therefore, when the ferroelectric film 6 has a thickness of 100 nm, the resistance per 1 cm2 of the ferroelectric film 6 is 107 xcexa9.
The ferroelectric film 6 and the gate electrode 7 have substantially the same area as shown in FIG. 4, and hence, the area of the ferroelectric film 6 and the gate electrode 7 is herein standardized to 1 cm2 so as to examine the electric characteristic of the ferroelectric memory.
FIG. 6 shows an equivalent circuit of the ferroelectric memory obtained when the gate electrode 7 and the silicon substrate 1 have the ground potential. In FIG. 6, Cox indicates the capacitance of the silicon oxide film 5, CF indicates the capacitance of the ferroelectric film 6 and RF indicates the internal resistance of the ferroelectric film 6. The value of Cox is 0.1 xcexc F/cm2 at most, which is substantially equal to the capacitance of a silicon oxide film of a standard MOS transistor, and the value of CF is 1 xcexc F/cm2. Therefore, the parallel capacitance of these capacitances is approximately 1 xcexc F/cm2. The value of RF is 107 xcexa9 as described above. Accordingly, the virtual floating potential at a point A in the equivalent circuit of FIG. 6 is exponentially lowered by discharging the capacitance Cox and the capacitance CF through the resistance RF. The time constant obtained in this case is (Cox+CF)xc3x97RF, that is, approximately 10 seconds. The actual time constant tends to be larger due to trapping in the gate electrode 7 and the shift from the ohm conductivity at a low voltage, and still, the upper limit of the time constant obtained through an experiment is 103 seconds at most.
This means that the bias voltage applied to the ferroelectric film 6 is lost so as to eliminate the conduction channel within approximately 103 seconds.
In order to practically use the ferroelectric memory as a nonvolatile memory, the data storage time is desired to be 10 years (=108 seconds) or more. In order to attain this data storage time, the resistivity of the ferroelectric film 6 needs to be increased to at least approximately 1020 xcexa9xc2x7cm, namely, to five or more figures.
However, a ferroelectric film with such large resistivity cannot be obtained at the present day, which hinders the practical use of a ferroelectric memory.
In consideration of the aforementioned circumstances, an object of the invention is providing a nonvolatile semiconductor memory capable of storing a data for a long period of time by suppressing loss of charge accompanied by a leakage current in a ferroelectric film.
In order to achieve the object, the first nonvolatile semiconductor memory of this invention comprises a source region and a drain region formed in a silicon substrate; a dielectric film formed above a region of the silicon substrate between the source region and the drain region; a ferroelectric film formed on the dielectric film; and a gate electrode formed on the ferroelectric film, and the ferroelectric film and the silicon substrate have a p-type conductivity, and the source region and the drain region have an n-type conductivity.
Also in order to achieve the object, the second nonvolatile semiconductor memory of this invention comprises a source region and a drain region formed in a silicon substrate; a dielectric film formed above a region of the semiconductor substrate between the source region and the drain region; a ferroelectric film formed on the dielectric film; and a gate electrode formed on the ferroelectric film, and the ferroelectric film and the silicon substrate have an n-type conductivity, and the source region and the drain region have a p-type conductivity.
In the first or second nonvolatile semiconductor memory of this invention, the ferroelectric film and the silicon substrate have the same conductivity type. Therefore, even when a bias voltage is applied to the ferroelectric film for writing a data, the loss of charge accompanied by a leakage current is minimally caused in the ferroelectric film because there are few carriers of charge with the same polarity as the bias voltage. Accordingly, a conduction channel formed in a surface portion of the silicon substrate can be kept for a long period of time and is constantly kept until an operation for eliminating the conduction channel is carried out. Also, after the operation for eliminating the conduction is carried out, the elimination of the conduction channel can be permanently kept.
As a result, a data can be stored for a long period of time in the first or second nonvolatile semiconductor memory of the invention.